Computer Architecture & Organization - 1

Register Transfer & Micro-Operation

Register - Collection of individual flip-flops connected in numbers to form different size of registers. Computer Registers are designated by CAPITAL LETTERS.

MAR - Memory Address Register
PC - Program Counter
IR - Instruction Register
R1 - Processor Register

Figure 1.1 : Block Diagram of the Register 

In Register Transfer Language, we can represent Register in various ways as above.

Micro-Operations - The operation executed on data stored in registers are called Micro-Operation. It is an elementary (basic) operation performed on the information stored in one or more registers. The results of the operation may replace the previous binary information of a register or may be transferred to another register. 

Register Transfer Language - It is the symbolic notation used to describe the micro-operation transfer among registers. It is a language of representing the transfer of data from one register to another register.

The term "Register Transfer " implies the availability of hardware logic circuit that can perform a stated micro-operation and transfer the result of the operation to the same or another register. 

A Register Transfer Language is a system for expressing in symbolic form the micro-operation sequences among the register of a digital module 

c = a + b

There are many micro-operations behind the screen like:

(i) Loading the data from Memory

(ii) Putting them in Processor Register

(iii) Loading the new data

(iv) Adding the data to the processor Register

(v) and storing back into the register.

Register Transfer - Information transfer from one register to another is designated in symbolic form by mean of a replacement operation is known as Register Transfer. The below statement R2 <- R1 

Figure 1.2 : Register Transfer

(i) Content of R1 Register is transferred to R2 Register.
(ii) Previous content of R2 Register would be overwritten by the content of R1 Register.
(iii) But that does not mean content of R1 would be deleted.

Figure 1.3 : Bit by Bit Transfer

In the above Figure 1.3 transfer will occur Bit by Bit from Right to Left, that means first Rightmost bit (bit 1 ) will be transfer from Register R1 to Register R2, then second bit from right (bit 0) will be transferred from Register R1 to Register R2 and so on.   

Register Transfer with Control Function -  Control Unit will transfer some signal to the register to perform the load operation or transfer operation. Normally, we want the transfer to occur only under a pre-determined control condition using if - then statement:

if (P = 1) then (R2<- R1)

Where P is a control signal generated in the control section. 

A Control Function is Boolean variable that is equal to 1 or 0. The control function is included in the statement as follows: 

P : R2 <- R1  

Figure 1.4 : Register Transfer with Control Function

(i) Load Input - Enable of R2 Register (Content of R1 Register would not be transferred)

(ii) Transfer will occur at time ( t+ 1) when signal is going to be low. At the end of the clock pulse, transfer will occur.  

Bus and Memory Transfer - We need to connect each of Register with individual Register such that information transfer occurs between these registers. A typical digital Computer has many registers and paths must be provided to transfer information from one register to another. The number of wires will be excessive if separate lines are used between each register and all other registers in the system.

Figure 1.5 : Individual Connection between Three Registers 

Now Consider, if Register D needs to be connected with all three more registers. So you can imagine, how much complex it will becomes. The solution for this is Common Bus System.

Figure 1.6 : 4 - Lines Common Bus  

(i) When input is given as 0 for both select line (S₀ and S₁).
(ii) 0th lines will be selected. Which means Register A will be selected (A Input is connected).
(iii) Input to the MUX will be A₃ A₂ A₁ A₀
(iv) Output will be A₃ A₂ A₁ A₀

The below table shows the Register that is selected by the bus for each of the four possible binary values of the select lines:

Table 1.1 : Register Selected as per Inputer Lines

In general,  a bus system will multiplex K registers of n bits each to produce an n-lines common bus. The number of multiplexers needed to construct the bus is equal to n, number of bits in each register. The size of each multiplexer must be k * 1, since it multiplexes k data lines.

(i) No. of Multiplexer - No. of Bits in Register
(ii) Size of Multiplexer - No. of Registers

For example a common bus for 8 Registers of 16 bits requires :
Multiplexers - 16 of ( 8 * 1)
Select Lines - 3
Output - 2³ (8 Lines Common Bus)

3- State Buffer - Buffer is having two states, One is Input state and another is Output state. Whatever we give the input we get the same is output but with some delay in the circuit. So buffer gates is used when we want to put some delay in logic circuits. 

We are having try-state buffer that means a buffer with three states. Two states are as usual - one is input, another is output with logic state either 0 or 1. Now we are adding one more state that is High Impedance State, Which makes to buffer gate work as open state circuit. 

Figure 1.7 : 3 - State Buffer

(i) The Control Input determines the output state. When the control input C = 1, the output is enabled and the gate behaves like any conventional buffer, with the output equals to the normal input.

(ii) When the control input C = 0, the output is disabled and the gate goes to a High - Impedance state regardless of the value in the normal input.

(iii) Which means, When control input C = 0, you would not get any output either your input is 0 or 1.

3- State Buffer is used for designing common bus system (like 4 - Line Common Bus). It can be designed using TriState buffer and the decoder.

Figure 1.8 Common Bus System using Tri-State Buffer and Decoder

In this case, we have taken signal bits A₀ B₀ C₀ D₀ . If we are having four bits register, we need to repeat this for A₁ B₁ C₁ D₁, A₂ B₂ C₂ D₂ and  A₃ B₃ C₃ D₃ also. 

(i) Consider  Select Line as S₁ – 1 and S₀ – 0

(ii) Output will be Line - 2 and rest lines will be 0. 

(iii) C₀ will be input and C₀ will be output. 

It is Single State, you can design n number of states depending upon the size of registers.